Connectors |
The DC power connector is designed to
mate with AMP part 1-480424 (using AMP pins P/N 350078-4).
Equivalent assignments are shown below, viewed from the end of the
drive. |
 |
| IDE connector |
The drive uses single-ended drivers and
receivers. The connector is designed to mate with 3M part 3417-7000
or equivalent. |
 |
| Notes: |
- A/T = IDE
- It is intended that the drive should only be in electrical
contact with the system chassis through the mounting holes.
Other electrical contact may degrade error rate performance.
As a result of this it is recommended that there should be
no metal contact to the drive except at the mounting holes
or the side rails into which the mounting holes are tapped.
|
Cabling |
The maximum cable length from the host
system to the drive, plus the circuit pattern length inside the host
systems, must not exceed 18 inches (45.7 cm).
For higher data transfer application
(>8.3 MB/sec) a consideration in system design is recommended to
reduce cable noise and/or cross-talk, such as; shorter cable, bus
termination, shielded cable, etc. |
Signal definition |
| |
| Notes: |
- "O" designates an output from the drive.
- "I" designates an input from the drive.
- "I/O" designates an input/output.
- "*" these signal lines are redifined during the
Ultra DMA protocol to provide special functions as detailed
in the table below.
|
| Interface |
The interface conforms to the working
document of information technology - AT attachment - 3 interface
(ATA-3) revision 6 dated October 26 1995 with following deviations. |
ICRCE (Interface CRC error)
Bit 7 of Error Rigister is supported as Interface CRC Error bit.
This bit will be set if a CRC error has occurred on the data bus
during an ULTRA-DMA transfer. |
Check power mode
Check Power Mode command returns FFh to the sector count register
when the drive is in idle mode. This command does not support 80h as
the return value. |
Sleep mode
During sleep mode the drive will be activated by any command,
including, but not limited to, a soft reset. |
Hard reset
Hard reset response is identical to a soft reset response with the
following exception: in a hard reset, the drive goes through the
Master/Slave handshake to determine if a slave is present, in a soft
reset this handshake does not occur. In a hard reset the Master
drive looks at the DASP line to determine if it is asserted
indicating a Slave is present. The Master drive also checks the
PDIAG line to see if the Slave has passed its internal diagnostics. |
Registers (primary channel
addresses) |
| Address |
Input register |
Output register |
| 1F0h |
data |
data |
| 1F1h |
error |
features |
| 1F2h |
sector count |
sector count |
1F3h
|
sector number
*LBA bits 0-7 |
sector number
*LBA bits 0-7 |
1F4h
|
cylinder low
*LBA bits 8-15 |
cylinder low
*LBA bits 8-15 |
1F5h
|
cylinder high
*LBA bits 16-23 |
cylinder high
*LBA bits 16-23 |
1F6h
|
drive/head
*LBA bits 24-27 |
drive/head
*LBA bits 24-27 |
| 1F7h |
status |
command |
| 3F6h |
alternate status |
device control |
| 3F7h |
drive address |
not used |
|
The host uses the register interface to
communicate to and from the drive. The registers are accessed
through the host port addresses shown. The host should not read or
write any registers when the Status Register BSY bit = 1. |
Note: *Meaning of register
contents when LBA addressing mode used. |
| |
